The present invention relates to a display system and a method of producing the same, and particularly to a display system in which an insulation layer with semiconductor light-emitting devices as light sources embedded therein is thinned and a conductor film is provided on upper end portions of the semiconductor light-emitting devices exposed by the thinning, whereby upper end portion electrodes are led out, and a method of producing the same.
As a method of leading out an electrode of a semiconductor device covered with an insulation layer to the exterior, a method of forming a contact hole in the insulation layer by lithography, embedding a conductor material in the contact hole by, for example, a sputtering method and forming a conductor film on the surface of the insulation layer is widely conducted.
FIG. 17 shows a process of leading out an electrode 51 in a semiconductor device 50. FIG. 17A is a sectional view showing a silicon substrate 52 provided with the electrode 51 and a SiO2 insulation layer 53 provided on the surface thereof. In order to lead out the electrode 51 to the upper side of the insulation layer 53, a contact hole 54 is formed at the location where the electrode 51 is present, as shown in FIG. 17B. At this time, a positional deviation may occur between the contact hole 54 and the electrode 51. Furthermore, the probability of a positional deviation is greater as the electrode 51 is made smaller.
In order to fill the contact hole 54 with a conductor metal and provide a lead-out electrode on the upper surface of the insulation layer 53, sputtering or vapor deposition of a conductor metal 55 such as aluminum is carried out. However, the straight flying characteristics of the conductor metal particles, the conductor metal 55 tends to be deposited on a bottom portion of the contact hole 54, but not on the side wall, because the side wall is hidden by the conductor metal 55 which is deposited and grown on the inner peripheral portion of the top opening of the contact hole 54, as shown in FIG. 17C. As the process proceeds, connection failure may occur at the side wall portion of the contact hole 54. Alternatively, there may be difficulty in closing the opening at the top of the contact hole while leaving cavity on the inside of the contact hole 54, as shown in FIG. 17D.
In order to facilitate the connection described above, a method is known in the prior art in which the insulation layer is etched back. Namely, in Japanese Patent Laid-open No. Hei 7-142579, a contact wiring is adopted in place of the contact hole. FIG. 18 shows a process of connecting a lower layer wiring and an upper layer wiring by a contact wiring in the case of producing an image display system including surface conduction type electron emitting devices (SCE) as elements. As shown in FIG. 18A, a metal is electron beam vapor deposited on the lower layer wiring 62 provided on an insulating substrate 61, and unrequired portions are lifted up to form the contact wiring 63. Subsequently, as shown in FIG. 18B, an insulation film 64 of silicon oxide or the like is formed over the entire surface by a sputtering method. Further, as shown in FIG. 18C, a photoresist 65 is formed over the entire surface. Thereafter, as shown in FIG. 18D, etching back for flattening is conducted to expose the surface of the contact wiring 63, and, as shown in FIG. 18E, an upper layer wiring 66 is provided. Thus, a multilayer wiring is disclosed. However, this method exposes the contact wiring, not the semiconductor light-emitting devices.
Japanese Patent Laid-open No. Hei 7-94124 discloses a method of producing light-emitting devices in a display system including electric field emission cathodes. As shown in FIG. 19A, a cathode chip 70a is provided on a main surface of a substrate 70, and, as shown in FIG. 19B, an insulation layer 72 and an anode layer 73 are sequentially provided on the substrate 70 by sputtering. Further, as shown in FIG. 19C, a fluorescent material layer 74 is provided by sputtering. Then, as shown in FIG. 19D, a polyimide resin layer 75 is deposited to cause flattening, and thereafter, the polyimide resin layer 75 is etched back to expose a protuberant portion of the fluorescent material layer 74, leaving the polyimide resin layer 75 therearound. Then, as shown in FIG. 19E, the fluorescent material layer 74, the anode layer 73 and the insulation layer 72 are sequentially selectively etched using the polyimide resin layer 75 as a mask, whereby the cathode chip 70a is exposed. However, this method has the exposure of the cathode chip itself as an object, and is not for leading out the upper end portion electrode of the semiconductor light-emitting device exposed.